The problem form Computer Engineering Department from Iraq using VHDL

A solution of problem #1:

First, we have to design the flip-flop JK as is shown in figures 1 and 2. 

After that, we have to design and connect the components with the flip-flop.

JK Flip Flop

Figure 1. True table.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity JK_Flop is

    Port ( J : in  STD_LOGIC;

           K : in  STD_LOGIC;

           clk : in  STD_LOGIC;

           Q : out  STD_LOGIC;

           QN : out  STD_LOGIC);

end JK_Flop;

architecture Behavioral of JK_Flop is

signal data: std_logic :='0';

Begin

process (clk, J, K) begin

  if (clk'event and clk = '1') then

    if(J='0' and K='0')then

    data <= data;

    elsif (J='1' and K='1')then

    data<= not data;

    elsif (J='0' and K='1')then

    data<= '0';

    else

    data<='1';

    end if;

  end if;

  end process;

  Q <= data;

  QN <= not data;

end Behavioral;

Figure 2. Flip-flop JK simulation.

Second:
The solution of problem #1 by top-level design.

------------------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity top_desing_1 is 
port (
RA: in std_logic;
RB: in std_logic;
clk: in std_logic;
EA, EB: out std_logic
);
end top_desing_1;

architecture Behavioral of top_desing_1 is

COMPONENT JK_Flop
PORT(
J : IN std_logic;
K : IN std_logic;
clk : IN std_logic;          
Q : OUT std_logic;
QN : OUT std_logic
);
END COMPONENT;

signal not_RA: std_logic;
signal not_RA_and_RB: std_logic;
signal not_RB: std_logic;
signal noty1: std_logic;

signal RA_or_RB: std_logic;
signal not_RA_and_not_RB: std_logic;
signal y2: std_logic;
signal not_y2: std_logic;

begin

not_RA_and_RB <= not_RA and RB;
not_RB <= not RB;

Inst_JK_Flop: JK_Flop PORT MAP(
not_RA_and_RB,--J
not_RB,--K
clk,
EB,--Q
noty1--QN 
);

not_RA <= not RA;
not_RB <= not RB;
RA_or_RB <= RA or RB;
not_RA_and_not_RB <= not_RA and not_RB;

Inst_JK_Flop2: JK_Flop PORT MAP(
RA_or_RB,--J
not_RA_and_not_RB,--K
clk,
y2,--Q
not_y2--QN 
);

EA <= noty1 and y2;

end Behavioral;


------------------------------------------------------------------------------------------------------------------
The solution by the RTL schematic is shown in figure 3.

Figure 3. RTL top design of problem1.

Shift register with a parallel load in VHDL

This program implements a shift register in VHDL. The register can be load with 8 bits which represents the data to be transmitted and the others bits that are attached to the data represent a protocol in this case the protocol is the RS-232.
Note: the most important line is :
reg <= reg(N-2 downto 0) & din; 
Where the & operand is to shift. It means that every clock the register content is going to shift to the left.
Figure 1 is the RTL circuit, figure 2 is the design at view technology schematic level. Finally, figure 3 is the testbench simulation of the code.

Figure 1. Shift register RTL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity shift_reg is
generic (N: integer := 12);
port ( clk, din, load: in std_logic;
data: in std_logic_vector(7 downto 0);
dout: out std_logic);
end shift_reg;

architecture Behavioral of shift_reg is

signal reg: std_logic_vector(N-1 downto 0):="100000000011";

begin
process(clk)begin
if clk'event and clk='1' then
if load = '1' then 
reg <= "10" & data & "11"; 
else
reg <= reg(N-2 downto 0) & din; 
end if;
end if;
end process;

dout <= reg(N-1);
end Behavioral;

Figure 2. View technology schematic.

Testbench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY shifth_reg_tb IS
END shifth_reg_tb;

ARCHITECTURE behavior OF shifth_reg_tb IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT shift_reg
    PORT(
         clk : IN  std_logic;
         din : IN  std_logic;
         load : IN  std_logic;
         data : IN  std_logic_vector(7 downto 0);
         dout : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal din : std_logic := '0';
   signal load : std_logic := '0';
   signal data : std_logic_vector(7 downto 0) := (others => '0');

  --Outputs
   signal dout : std_logic;

   -- Clock period definitions
   constant clk_period : time := 20 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
   uut: shift_reg PORT MAP (
          clk => clk,
          din => din,
          load => load,
          data => data,
          dout => dout
        );

   -- Clock process definitions
   clk_process :process
   begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
   end process;

process 
begin
load <= '1';
wait for clk_period;
load <= '0';
wait for clk_period*15;
end process;


data <= "11001100", "00001111" after 300 ns;
din <= '1' , '1' after 1000 ns;
END;

Figure 3. Testbench simulation.

Automated delay in VHDL

This code is an example to design an automatic delay:

First we have to calculate the number of the clocks needed to achieve a period. Then with the numbers of cloks (nclks) the length of the counter (N) can be calculated as log2(nclks).

Finally we use generic to define N. 

Also is good to mentioned that no reset is used due to the tick signal is initialized with the highest value using others =>'1', therfore when the fist clock is rising edge the tick signal is going to be 0 and then the tick signal is going to be incremented by one in each clock.

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity delay is

generic (n: integer := 8); --number of bits

port ( clk: in std_logic;

   delay_out: out std_logic);

end delay;

architecture behavioral of delay is

signal tick: std_logic_vector(n-1 downto 0) := (others =>'1');

constant nclks: integer := 128;

begin

  process (clk) begin

   if clk'event and clk = '1' then

    if tick < nclks-1 then

     tick <= tick + 1;

    else

     tick <= (others => '0');

     end if;

   end if;

  end process;

 delay_out <= '1' when (tick < (nclks/2)) else '0'; 

end behavioral;

Clock divider in VHDL

This program divides the clock frecuency from 50Mhz to 25 MHz implementing the circuit shown in figure 1.

Finally the simulation of the code is shown in figure 2.

Figure 1. RTL of clock divider.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity clk_div is

port ( clk: in std_logic;

  q: out std_logic);

 

end clk_div;

architecture Behavioral of clk_div is

signal x: std_logic :='0';

begin

  process(clk)begin

  if clk'event and clk='1' then

  x <= not x;

  end if;

  end process;

  q<=x;

end Behavioral;

Figure 2. Clock div simulation.

Counters in VHDL

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter is

port ( clk, reset: in std_logic;

  d: out std_logic_vector(3 downto 0));

end counter;

architecture Behavioral of counter is

signal x: std_logic_vector(3 downto 0);

Begin

  process(clk) begin

  if reset = '1' then

  x <= "0000";

  elsif clk'event and clk = '1' then

  x <= x+1;

  end if; 

  end process;

  d <= x;

end Behavioral;

Registers in cascade

This program implements two registers in cascade within a process in VHDL. 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity cascade_reg is

port (clk: in std_logic;

  d: in std_logic;

  q: out std_logic);

end cascade_reg;

architecture Behavioral of cascade_reg is

signal n1: std_logic;

begin

  process (clk) begin

  if clk'event and clk = '1' then

  n1 <= d;

  q <= n1;

  end if;

  end process;

end Behavioral;

Synchronous reset register in VHDL & Testbench 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity asyncro_reg is
port( clk, reset: in std_logic;
d: in std_logic_vector(3 downto 0);
q: out std_logic_vector(3 downto 0));
end asyncro_reg;

architecture Behavioral of asyncro_reg is

begin

process (clk, reset) begin
if clk'event and clk = '1' then
if reset = '1' then
q <= "0000";
else
q <= d;
end if;
end if;
end process;

end Behavioral;

-----------------------TESTBENCH------------------------------------

--------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

 

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

 

ENTITY asyncro_register IS

END asyncro_register;

 

ARCHITECTURE behavior OF asyncro_register IS 

 

    -- Component Declaration for the Unit Under Test (UUT)

 

    COMPONENT asyncro_reg

    PORT(

         clk : IN  std_logic;

         reset : IN  std_logic;

         d : IN  std_logic_vector(3 downto 0);

         q : OUT  std_logic_vector(3 downto 0)

        );

    END COMPONENT;

    

   --Inputs

   signal clk : std_logic := '0';

   signal reset : std_logic := '0';

   signal d : std_logic_vector(3 downto 0) := (others => '0');

  --Outputs

   signal q : std_logic_vector(3 downto 0);

   -- Clock period definitions

   constant clk_period : time := 20 ns;

 

BEGIN

 

-- Instantiate the Unit Under Test (UUT)

   uut: asyncro_reg PORT MAP (

          clk => clk,

          reset => reset,

          d => d,

          q => q

        );

   -- Clock process definitions

   clk_process :process

   begin

loop

clk <= '1';

wait for clk_period/2;

clk <= '0';

wait for clk_period/2;

end loop;

   end process;

 

reset <= '1', '0' after 60 ns;

d <= "1111", "0000" after 100 ns;

   

END;

Resettable Registers in VHDL

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity flopr is

port( clk, reset: in std_logic;

d: in std_logic_vector(3 downto 0);

q: out std_logic_vector(3 downto 0));

end flopr;

architecture Behavioral of flopr is

begin

  process (clk, reset) begin

  if reset = '1' then

  q <= "0000";

  elsif clk' event and clk = '1' then

  q <= d;

  end if;

  end process;

end Behavioral;