Clock divider in VHDL

This program divides the clock frecuency from 50Mhz to 25 MHz implementing the circuit shown in figure 1.

Finally the simulation of the code is shown in figure 2.

Figure 1. RTL of clock divider.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity clk_div is

port ( clk: in std_logic;

  q: out std_logic);

 

end clk_div;

architecture Behavioral of clk_div is

signal x: std_logic :='0';

begin

  process(clk)begin

  if clk'event and clk='1' then

  x <= not x;

  end if;

  end process;

  q<=x;

end Behavioral;

Figure 2. Clock div simulation.