Resettable Registers in VHDL

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity flopr is

port( clk, reset: in std_logic;

d: in std_logic_vector(3 downto 0);

q: out std_logic_vector(3 downto 0));

end flopr;

architecture Behavioral of flopr is

begin

  process (clk, reset) begin

  if reset = '1' then

  q <= "0000";

  elsif clk' event and clk = '1' then

  q <= d;

  end if;

  end process;

end Behavioral;