Shift register with a parallel load in VHDL

This program implements a shift register in VHDL. The register can be load with 8 bits which represents the data to be transmitted and the others bits that are attached to the data represent a protocol in this case the protocol is the RS-232.
Note: the most important line is :
reg <= reg(N-2 downto 0) & din; 
Where the & operand is to shift. It means that every clock the register content is going to shift to the left.
Figure 1 is the RTL circuit, figure 2 is the design at view technology schematic level. Finally, figure 3 is the testbench simulation of the code.

Figure 1. Shift register RTL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity shift_reg is
generic (N: integer := 12);
port ( clk, din, load: in std_logic;
data: in std_logic_vector(7 downto 0);
dout: out std_logic);
end shift_reg;

architecture Behavioral of shift_reg is

signal reg: std_logic_vector(N-1 downto 0):="100000000011";

begin
process(clk)begin
if clk'event and clk='1' then
if load = '1' then 
reg <= "10" & data & "11"; 
else
reg <= reg(N-2 downto 0) & din; 
end if;
end if;
end process;

dout <= reg(N-1);
end Behavioral;

Figure 2. View technology schematic.

Testbench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY shifth_reg_tb IS
END shifth_reg_tb;

ARCHITECTURE behavior OF shifth_reg_tb IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT shift_reg
    PORT(
         clk : IN  std_logic;
         din : IN  std_logic;
         load : IN  std_logic;
         data : IN  std_logic_vector(7 downto 0);
         dout : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal din : std_logic := '0';
   signal load : std_logic := '0';
   signal data : std_logic_vector(7 downto 0) := (others => '0');

  --Outputs
   signal dout : std_logic;

   -- Clock period definitions
   constant clk_period : time := 20 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
   uut: shift_reg PORT MAP (
          clk => clk,
          din => din,
          load => load,
          data => data,
          dout => dout
        );

   -- Clock process definitions
   clk_process :process
   begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
   end process;

process 
begin
load <= '1';
wait for clk_period;
load <= '0';
wait for clk_period*15;
end process;


data <= "11001100", "00001111" after 300 ns;
din <= '1' , '1' after 1000 ns;
END;

Figure 3. Testbench simulation.