Counters in VHDL

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter is

port ( clk, reset: in std_logic;

  d: out std_logic_vector(3 downto 0));

end counter;

architecture Behavioral of counter is

signal x: std_logic_vector(3 downto 0);

Begin

  process(clk) begin

  if reset = '1' then

  x <= "0000";

  elsif clk'event and clk = '1' then

  x <= x+1;

  end if; 

  end process;

  d <= x;

end Behavioral;