Automated delay in VHDL

This code is an example to design an automatic delay:

First we have to calculate the number of the clocks needed to achieve a period. Then with the numbers of cloks (nclks) the length of the counter (N) can be calculated as log2(nclks).

Finally we use generic to define N. 

Also is good to mentioned that no reset is used due to the tick signal is initialized with the highest value using others =>'1', therfore when the fist clock is rising edge the tick signal is going to be 0 and then the tick signal is going to be incremented by one in each clock.

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity delay is

generic (n: integer := 8); --number of bits

port ( clk: in std_logic;

   delay_out: out std_logic);

end delay;

architecture behavioral of delay is

signal tick: std_logic_vector(n-1 downto 0) := (others =>'1');

constant nclks: integer := 128;

begin

  process (clk) begin

   if clk'event and clk = '1' then

    if tick < nclks-1 then

     tick <= tick + 1;

    else

     tick <= (others => '0');

     end if;

   end if;

  end process;

 delay_out <= '1' when (tick < (nclks/2)) else '0'; 

end behavioral;