Synchronous reset register in VHDL & Testbench 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity asyncro_reg is
port( clk, reset: in std_logic;
d: in std_logic_vector(3 downto 0);
q: out std_logic_vector(3 downto 0));
end asyncro_reg;

architecture Behavioral of asyncro_reg is

begin

process (clk, reset) begin
if clk'event and clk = '1' then
if reset = '1' then
q <= "0000";
else
q <= d;
end if;
end if;
end process;

end Behavioral;

-----------------------TESTBENCH------------------------------------

--------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

 

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

 

ENTITY asyncro_register IS

END asyncro_register;

 

ARCHITECTURE behavior OF asyncro_register IS 

 

    -- Component Declaration for the Unit Under Test (UUT)

 

    COMPONENT asyncro_reg

    PORT(

         clk : IN  std_logic;

         reset : IN  std_logic;

         d : IN  std_logic_vector(3 downto 0);

         q : OUT  std_logic_vector(3 downto 0)

        );

    END COMPONENT;

    

   --Inputs

   signal clk : std_logic := '0';

   signal reset : std_logic := '0';

   signal d : std_logic_vector(3 downto 0) := (others => '0');

  --Outputs

   signal q : std_logic_vector(3 downto 0);

   -- Clock period definitions

   constant clk_period : time := 20 ns;

 

BEGIN

 

-- Instantiate the Unit Under Test (UUT)

   uut: asyncro_reg PORT MAP (

          clk => clk,

          reset => reset,

          d => d,

          q => q

        );

   -- Clock process definitions

   clk_process :process

   begin

loop

clk <= '1';

wait for clk_period/2;

clk <= '0';

wait for clk_period/2;

end loop;

   end process;

 

reset <= '1', '0' after 60 ns;

d <= "1111", "0000" after 100 ns;

   

END;