Registers in cascade

This program implements two registers in cascade within a process in VHDL. 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity cascade_reg is

port (clk: in std_logic;

  d: in std_logic;

  q: out std_logic);

end cascade_reg;

architecture Behavioral of cascade_reg is

signal n1: std_logic;

begin

  process (clk) begin

  if clk'event and clk = '1' then

  n1 <= d;

  q <= n1;

  end if;

  end process;

end Behavioral;