Flip-Flop in VHDL

This program is an example of Flip-flop implementation in VHDL.
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library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity flop is

port (clk: in STD_LOGIC;

d: in STD_LOGIC_VECTOR (3 downto 0) ;

q: out STD_LOGIC_VECTOR (3 downto 0)) ;

end;

architecture synth of flop is

begin

  process (clk) begin

  if clk'event and clk = '1' then

  q <= d;

  end if;

  end process;

end;

BCD-to-SSD converter

This program implements the binary to seven segment decoder in VHDL.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity bcd_to_ssd is

port(

x: in std_logic_vector(3 downto 0);

output: out std_logic_vector(6 downto 0));

end bcd_to_ssd;

architecture Behavioral of bcd_to_ssd is

begin

process(x)

begin

  case x is

  when "0000" => output <= "1111110"; --decimal 126

  when "0001" => output <= "0110000"; --decimal 48

  when "0010" => output <= "1101101"; --decimal 109

  when "0011" => output <= "1111001"; --decimal 121

  when "0100" => output <= "0110011"; --decimal 51

  when "0101" => output <= "1011011"; --decimal 91

  when "0110" => output <= "1011111"; --decimal 95

  when "0111" => output <= "1110000"; --decimal 112

  when "1000" => output <= "1111111"; --decimal 127

  when "1001" => output <= "1111011"; --decimal 123

  when others => output <= "1001111";--letter"e"(error)-> decimal 79

  end case;

end process;

end Behavioral;

Arithmetic-logic unit (ALU) in VHDL

This program shows how to implement an ALU in VHDL.

library IEEE; 

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity alu is

port (a, b: in std_logic_vector(7 downto 0);

cin: in std_logic;

opcode: in std_logic_vector(3 downto 0);

y: out std_logic_vector(7 downto 0)

);

end alu;

architecture behavioral of alu is

begin

  with opcode select

  -----logic part:------

  y <= a when "0000",

  not a when "0001",

  b when "0010",

  not b when "0011",

  a and b when "0100",

  a nand b when "0101",

  a or b when "0110",

  a nor b when "0111",

  -----arithmetic part:------

  a+1 when "1000",

  b+1 when "1001",

  a+b when "1010",

  a-b when "1011",

  0-a+b when "1100",

  0-a-b when "1101",

  a+b+1 when "1110",

  a+b+cin when others;

end behavioral;

True table in VHDL

Implement the following true table in VHDL.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity true_table is

port (a, b, c : in std_logic;

f: out std_logic);

end true_table;

architecture Behavioral of true_table is

begin

  f <= '1' when (a = '0' and b= '0' and b= '0') else

    '1' when (a = '0' and b= '1' and b= '1') else

    '1' when (a = '1' and b= '0' and b= '0') else

    '1' when (a = '1' and b= '1' and b= '1') else

    '0';

end Behavioral;

Address Decoder

This program is an example of decoder using the when else sentence in VHDL.

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity address_decoder is

port ( x: in std_logic_vector(2 downto 0);

  y: out std_logic_vector(7 downto 0));

end address_decoder;

architecture Behavioral of address_decoder is

begin

  y <= "00000001" when x = "000" else

  "00000010" when x = "001" else

  "00000100" when x = "010" else

  "00001000" when x = "011" else

  "00010000" when x = "100" else

  "00100000" when x = "101" else

  "01000000" when x = "110" else

  "10000000";

end Behavioral;

Hierarchical design

In this example, a 2-input digital adder, input carry and output sum are first designed.
The adder is then used to build a complete adder using the component and port directives. In addition generic is used to atomize the design for N inputs.

Dr. Carlos Hernandez. Any comment you can contact me at: postgraduatecahg@gmail.com
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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity full_adder is

port (a, b, cin: in std_logic;

s, cout: out std_logic);

end full_adder;

architecture Behavioral of full_adder is

begin

  s<= a xor b xor cin;

  cout <= (a and b) or (a and cin) or (b and cin);

end Behavioral;

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity carry_ripple_adder is

generic (N: integer := 8); --number of bits

PORT (a, b: in std_logic_vector(N-1 downto 0);

cin: in std_logic;

s: out std_logic_vector(N-1 downto 0);

cout: out std_logic);

end carry_ripple_adder;

architecture Behavioral of carry_ripple_adder is

signal carry: std_logic_vector(N downto 0);

component full_adder is

port (a, b, cin: in std_logic;

s, cout: out std_logic);

end component;

begin

carry(0) <= cin;

gen_adder: for i in a'RANGE generate

FA: full_adder port map (a(i), b(i), carry(i), s(i), carry(i+1));

end generate;

cout <= carry(N);

end Behavioral;

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UART ARM Cortex M4 (Tiva C) 

/*
This program configures the UART to work with a bit-rate of 115200 bits/seconds.
The system clock is configured to work at 80MHz assisted by PLL.
We first define all register to configure the UART and then perform functions to send and read characters and strings.
*/

#include "TM4C123.h"                    // Device header

// configure the system to get its clock from the PLL

#define SYSCTL_RIS_R            (*((volatile unsigned long *)0x400FE050))
#define SYSCTL_RCC_R            (*((volatile unsigned long *)0x400FE060))
#define SYSCTL_RCC2_R           (*((volatile unsigned long *)0x400FE070))

// Define UART registers
#define GPIO_PORTA_AFSEL_R      (*((volatile unsigned long *)0x40004420))
#define GPIO_PORTA_DEN_R        (*((volatile unsigned long *)0x4000451C))
#define GPIO_PORTA_AMSEL_R      (*((volatile unsigned long *)0x40004528))
#define GPIO_PORTA_PCTL_R       (*((volatile unsigned long *)0x4000452C))
#define UART0_DR_R              (*((volatile unsigned long *)0x4000C000))
#define UART0_FR_R              (*((volatile unsigned long *)0x4000C018))
#define UART0_IBRD_R            (*((volatile unsigned long *)0x4000C024))
#define UART0_FBRD_R            (*((volatile unsigned long *)0x4000C028))
#define UART0_LCRH_R            (*((volatile unsigned long *)0x4000C02C))
#define UART0_CTL_R             (*((volatile unsigned long *)0x4000C030))
#define UART_FR_TXFF            0x00000020  // UART Transmit FIFO Full
#define UART_FR_RXFE            0x00000010  // UART Receive FIFO Empty

#define SYSCTL_RCGC1_R          (*((volatile unsigned long *)0x400FE104))
#define SYSCTL_RCGC2_R          (*((volatile unsigned long *)0x400FE108))


void PLL_Init(void);
void UART_Init(void);
void UART_Char_Output(unsigned char data);
unsigned char UART_Char_Input(void);
void UART_Write_String(char *p);

__asm void
Delay(unsigned long n)
{
    SUBS    R0, #1
    BNE     Delay
    BX      LR ;//the link register is providing the address to //branch to.
}

int main(void){  
  PLL_Init();
  UART_Init();

  while(1){

    UART_Char_Output('a');
    Delay(13333333);           // delay ~0.5 sec at 80 MHz

while(UART_Char_Input()!='b');
UART_Write_String("you pressed the character b");
    
}
}


void PLL_Init(void){
  // 0) Use RCC2
  SYSCTL_RCC2_R |=  0x80000000;  // USERCC2
  // 1) bypass PLL while initializing
  SYSCTL_RCC2_R |=  0x00000800;  // BYPASS2, PLL bypass
  // 2) select the crystal value and oscillator source
  SYSCTL_RCC_R = (SYSCTL_RCC_R &~0x000007C0)   // clear XTAL field, bits 10-6
                 + 0x00000540;   // 10101, configure for 16 MHz crystal
  SYSCTL_RCC2_R &= ~0x00000070;  // configure for main oscillator source 10001111
  // 3) activate PLL by clearing PWRDN
  SYSCTL_RCC2_R &= ~0x00002000;
  // 4) set the desired system divider
  SYSCTL_RCC2_R |= 0x40000000;   // use 400 MHz PLL, DIV400
  SYSCTL_RCC2_R = (SYSCTL_RCC2_R&~ 0x1FC00000)  // clear system clock divider
                  + (4<<22);      // configure for 80 MHz clock,  400/(4+1) = 80MHz
  // 5) wait for the PLL to lock by polling PLLLRIS
  while((SYSCTL_RIS_R&0x00000040)==0){};  // wait for PLLRIS bit
  // 6) enable use of PLL by clearing BYPASS
  SYSCTL_RCC2_R &= ~0x00000800;
}

void UART_Init(void){
  SYSCTL_RCGC1_R |= 0x01; // activate UART0
  SYSCTL_RCGC2_R |= 0x01; // activate port A
  UART0_CTL_R &= ~0x01;   // disable UART
  UART0_IBRD_R = 43;   // IBRD = int(80,000,000 / (16 * 115,200)) = int(43.40278)
  UART0_FBRD_R = 26;      // FBRD = round(0.40278 * 64) = 26
  // 8 bit word length (no parity bits, one stop bit, FIFOs)
  UART0_LCRH_R = 0x70;// 0x01110000 
  //UART0_CTL_R |= UART_CTL_UARTEN;  // enable UART,  0x00000001  // UART Enable
  UART0_CTL_R |= 0x01;       // enable UART,  0x00000001  // UART Enable
  GPIO_PORTA_AFSEL_R |= 0x03;           // enable alt funct on PA1-0
  GPIO_PORTA_DEN_R |= 0x03;             // enable digital I/O on PA1-0
                                        // configure PA1-0 as UART
  GPIO_PORTA_PCTL_R = (GPIO_PORTA_PCTL_R&0xFFFFFF00)+0x00000011;
  GPIO_PORTA_AMSEL_R &= ~0x03;          // disable analog functionality on PA
}

void UART_Char_Output(unsigned char data){
  while((UART0_FR_R & UART_FR_TXFF) != 0);
  UART0_DR_R = data;
}

unsigned char UART_Char_Input(void){
  while((UART0_FR_R & UART_FR_RXFE) != 0);
  return((unsigned char)(UART0_DR_R & 0xFF));
}

void UART_Write_String(char *p){
  while(*p){
    UART_Char_Output(*p);
    p++;
  }
}