Hierarchical design

In this example, a 2-input digital adder, input carry and output sum are first designed.
The adder is then used to build a complete adder using the component and port directives. In addition generic is used to atomize the design for N inputs.

Dr. Carlos Hernandez. Any comment you can contact me at: postgraduatecahg@gmail.com
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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity full_adder is

port (a, b, cin: in std_logic;

s, cout: out std_logic);

end full_adder;

architecture Behavioral of full_adder is

begin

  s<= a xor b xor cin;

  cout <= (a and b) or (a and cin) or (b and cin);

end Behavioral;

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity carry_ripple_adder is

generic (N: integer := 8); --number of bits

PORT (a, b: in std_logic_vector(N-1 downto 0);

cin: in std_logic;

s: out std_logic_vector(N-1 downto 0);

cout: out std_logic);

end carry_ripple_adder;

architecture Behavioral of carry_ripple_adder is

signal carry: std_logic_vector(N downto 0);

component full_adder is

port (a, b, cin: in std_logic;

s, cout: out std_logic);

end component;

begin

carry(0) <= cin;

gen_adder: for i in a'RANGE generate

FA: full_adder port map (a(i), b(i), carry(i), s(i), carry(i+1));

end generate;

cout <= carry(N);

end Behavioral;

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