Arithmetic-logic unit (ALU) in VHDL

This program shows how to implement an ALU in VHDL.

library IEEE; 

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity alu is

port (a, b: in std_logic_vector(7 downto 0);

cin: in std_logic;

opcode: in std_logic_vector(3 downto 0);

y: out std_logic_vector(7 downto 0)

);

end alu;

architecture behavioral of alu is

begin

  with opcode select

  -----logic part:------

  y <= a when "0000",

  not a when "0001",

  b when "0010",

  not b when "0011",

  a and b when "0100",

  a nand b when "0101",

  a or b when "0110",

  a nor b when "0111",

  -----arithmetic part:------

  a+1 when "1000",

  b+1 when "1001",

  a+b when "1010",

  a-b when "1011",

  0-a+b when "1100",

  0-a-b when "1101",

  a+b+1 when "1110",

  a+b+cin when others;

end behavioral;