True table in VHDL

Implement the following true table in VHDL.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity true_table is

port (a, b, c : in std_logic;

f: out std_logic);

end true_table;

architecture Behavioral of true_table is

begin

  f <= '1' when (a = '0' and b= '0' and b= '0') else

    '1' when (a = '0' and b= '1' and b= '1') else

    '1' when (a = '1' and b= '0' and b= '0') else

    '1' when (a = '1' and b= '1' and b= '1') else

    '0';

end Behavioral;