PS2 protocol implementation for a keyboard using VHDL

This is a sample of my course of FPGAs & VHDL.

If you interested in the complete course or you need help with a project. You can contact me at:

postgraduatecahg@gmail.com

Figure 1. PS2-Keyboard.

Figure 2. PS2 Protocol.

Explanation of the following code.

First is important to note that data is captured approximately every falling edge clock. Thus we use clk'event and clk=0.

Then, this protocol presents an advantage which is that the keyboard sends the clock signal, as a result, we can read a data every clock by a shift register. The frame is composed of 22 bits which are divided into two parts. The first 11 bits are the information and the second 11 bits are the acknowledge byte. The acknowledge byte in hexadecimal format is X"F0", this byte is sent in the second byte if the key is acknowledged. 

Therefore the program evaluates if the second byte is X"F0" and then assign the data byte to leds on my FPGA board as is seen below.

if (clk'event and clk ='1' and data_frame(8 downto 1)= X"F0") then

    leds <= data_frame(19 downto 12);

VHDL Program.

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity keyboard is
    Port ( clk,data: in std_logic;
           leds : out std_logic_vector(7 downto 0));
end keyboard;

architecture keyboard_Architecture of keyboard is
signal data_frame: std_logic_vector(21 downto 0);

begin

process (clk, data, data_frame)
begin
if clk'event and clk ='0' then
    data_frame <= data &  data_frame(21 downto 1);
end if;
end process;


process (clk,data_frame)
begin
if (clk'event and clk ='1' and data_frame(8 downto 1)= X"F0") then
    leds <= data_frame(19 downto 12);  
end if;
end process;

end keyboard_Architecture;

UCF file

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NET "clk"      LOC = "R12" | CLOCK_DEDICATED_ROUTE = FALSE;

NET "data"     LOC = "P11" | IOSTANDARD = LVCMOS33 ;

NET "leds<0>"  LOC = "J14" | IOSTANDARD = LVTTL  | DRIVE = 8  | SLEW = SLOW ;
NET "leds<1>"  LOC = "J15" | IOSTANDARD = LVTTL  | DRIVE = 8  | SLEW = SLOW ;
NET "leds<2>"  LOC = "K15" | IOSTANDARD = LVTTL  | DRIVE = 8  | SLEW = SLOW ;
NET "leds<3>"  LOC = "K14" | IOSTANDARD = LVTTL  | DRIVE = 8  | SLEW = SLOW ;
NET "leds<4>"  LOC = "E17" | IOSTANDARD = LVTTL  | DRIVE = 8  | SLEW = SLOW ;
NET "leds<5>"  LOC = "P15" | IOSTANDARD = LVTTL  | DRIVE = 8  | SLEW = SLOW ;
NET "leds<6>"  LOC = "F4"  | IOSTANDARD = LVTTL  | DRIVE = 8  | SLEW = SLOW ;
NET "leds<7>"  LOC = "R4"  | IOSTANDARD = LVTTL  | DRIVE = 8  | SLEW = SLOW ;