The finite state machine in VHDL

In this sample, I show how to implement a finite state machine.
In the code, an asynchronous reset is implemented first. After that tow logic parts are implemented, the first logic part is for flow program or in other words the flow of state. The second logic part is for output logic.
Finally is important to know that key part is type statetype which states the implementation of the state machine.

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity FSM1 is

port(

clk, reset: in std_logic;

y: out std_logic);

end FSM1;

architecture Behavioral of FSM1 is

type statetype is (S0, S1, S2);

signal state, nextstate: statetype;

-- state register part

begin

process (clk, reset) begin

  if (reset='1') then

  state <= S0;

  elsif (clk'event and clk='1') then

  state <= nextstate;

  end if;

end process;

-- Next state logic

  nextstate <= S1 when state = S0 else

     S2 when state = S1 else

     S0;

-- Output logic

y <= '1' when state = S0 else '0';

end Behavioral;