Mealy finite state machine implemented in VHDL

In this sample the I implement the Mealy finite state machine using VHDL.

It is important to keep in mind that in the Mealy machine the output depends on the states and the inputs, in this case, the input a (see figure 2).

Finally, this post is based on the book Digital design and computer architecture by David Harris.

  

Remember that I can teach you on linea or help you in your projects as a consultant.

if you interested ask to:

postgraduatecahg@gmail.com 

Figure 1. State flow diagram.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity mealy is

port(clk, reset: in std_logic;

a: in std_logic;

y: out std_logic);

end mealy;

architecture Behavioral of mealy is

type statetype is (S0, S1, S2, S3);

signal state, nextstate: statetype;

begin

-- state register

process (clk, reset)begin

  if reset = '1' then

  state <=S0;

  elsif clk'event and clk='1' then

  state <= nextstate;

  end if;

end process;

-- next state logic

process (state, a) begin

  case state is

  when S0 =>

  if a = '1' then

  nextstate <= S1;

  else

  nextstate <= S0;

  end if;

 

  when S1 =>

  if a = '1' then

  nextstate <= S2;

  else

  nextstate <= S0;

  end if;

 

  when S2 =>

  if a = '1' then

  nextstate <= S2;

  else

  nextstate <= S3;

  end if;

 

  when S3 =>

  if a = '1' then

  nextstate <= S1;

  else

  nextstate <= S0;

  end if;

 

  when others => nextstate <= S0;

  end case;

end process;

-- Output logic

y <= '1' when (a='1' and state = S3) else '0';

end Behavioral;

Figure 2. RTL of the Mealy FSM.

Figure 3. Simulation of Mealy FSM.