Buffered Mux

This program is a sample of mux design using VHDL

Any comment you can contact me at: 

postgraduatecagh@gmail.com

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity buffered_mux is

  port (

  a, b, c, d: in std_logic_vector(7 downto 0);

  sel: in std_logic_vector(1 downto 0);

  enable: in std_logic;

  y: out std_logic_vector (7 downto 0));

end buffered_mux;

architecture Behavioral of buffered_mux is

signal x: std_logic_vector (7 downto 0);

begin

  x <= a when sel = "00" else --

  b when sel = "01" else

  c when sel = "10" else

  d;

 

  y <= x when enable = '1' else

  (others =>'Z');

 

end Behavioral;