PLL (phase lock loop)

/*
*******************************************************************************************************
This program configures the PLL to operates at 80 MHz.
Therefore the system clock is runing at 80 MHz insted of 16 MHz.
*/

/* ***************************************************************************************************** 
These addresses define the registers that configure the PLL
*/

#define SYSCTL_RIS_R  (*((volatile unsigned long *)0x400FE050))
#define SYSCTL_RCC_R  (*((volatile unsigned long *)0x400FE060))
#define SYSCTL_RCC2_R (*((volatile unsigned long *)0x400FE070))

// The end of PLL registers definition.

#define GPIO_PORTF_DATA_R (*((volatile unsigned long *)0x400253FC))
#define GPIO_PORTF_DIR_R  (*((volatile unsigned long *)0x40025400))
#define GPIO_PORTF_AFSEL_R (*((volatile unsigned long *)0x40025420))
#define GPIO_PORTF_PUR_R   (*((volatile unsigned long *)0x40025510))
#define GPIO_PORTF_DEN_R   (*((volatile unsigned long *)0x4002551C))
#define GPIO_PORTF_LOCK_R  (*((volatile unsigned long *)0x40025520))
#define GPIO_PORTF_CR_R    (*((volatile unsigned long *)0x40025524))
#define GPIO_PORTF_AMSEL_R (*((volatile unsigned long *)0x40025528))
#define GPIO_PORTF_PCTL_R  (*((volatile unsigned long *)0x4002552C))
#define SYSCTL_RCGC2_R     (*((volatile unsigned long *)0x400FE108))


void PortF_Init(void);
void PLL_Init(void);

__asm void
Delay(unsigned long n)
{
    SUBS    R0, #1
    BNE     Delay
    bx      LR ;//the link register is providing the address to branch to.
}

int main(void){  
  PLL_Init();
PortF_Init();
  
  while(1){
    GPIO_PORTF_DATA_R |= 0x08;
    Delay(13333333);           // delay ~0.5 sec at 80 MHz
    GPIO_PORTF_DATA_R &= ~0x08;
    Delay(13333333);           // delay ~0.5 sec at 80 MHz
}
}

void PortF_Init(void){ 
  volatile unsigned long delay;
  SYSCTL_RCGC2_R |= 0x00000020;     // 1) F clock
  delay = SYSCTL_RCGC2_R;           // delay   
  GPIO_PORTF_LOCK_R = 0x4C4F434B;   // 2) unlock PortF PF0  
  GPIO_PORTF_CR_R |= 0x1F;           // allow changes to PF4-0       
  GPIO_PORTF_AMSEL_R &= 0x00;        // 3) disable analog function
  GPIO_PORTF_PCTL_R &= 0x00000000;   // 4) GPIO clear bit PCTL  
  GPIO_PORTF_DIR_R &= ~0x11;         // 5.1) PF4,PF0 input, 
  GPIO_PORTF_DIR_R |= 0x08;        // 5.2) PF3 output  
  GPIO_PORTF_AFSEL_R &= 0x00;     // 6) no alternate function
  GPIO_PORTF_PUR_R |= 0x11;   // enable pullup resistors on PF4,PF0       
  GPIO_PORTF_DEN_R |= 0x1F;     // 7) enable digital pins PF4-PF0     }

void PLL_Init(void){
  // 0) Use RCC2
  SYSCTL_RCC2_R |=  0x80000000;  // USERCC2
  // 1) bypass PLL while initializing
  SYSCTL_RCC2_R |=  0x00000800;  // BYPASS2, PLL bypass
  // 2) select the crystal value and oscillator source
  SYSCTL_RCC_R = (SYSCTL_RCC_R &~0x000007C0)   
 // clear XTAL field, bits 10-6  + 0x00000540;   
 // 10101, configure for 16 MHz crystal
  SYSCTL_RCC2_R &= ~0x00000070;  // configure for main oscillator source 10001111
  // 3) activate PLL by clearing PWRDN
  SYSCTL_RCC2_R &= ~0x00002000;
  // 4) set the desired system divider
  SYSCTL_RCC2_R |= 0x40000000;   // use 400 MHz PLL, DIV400
  SYSCTL_RCC2_R = (SYSCTL_RCC2_R&~ 0x1FC00000)  // clear system clock divider
                  + (4<<22);      // configure for 80 MHz clock,  400/(4+1) = 80MHz
  // 5) wait for the PLL to lock by polling PLLLRIS
  while((SYSCTL_RIS_R&0x00000040)==0){};  // wait for PLLRIS bit
  // 6) enable use of PLL by clearing BYPASS
  SYSCTL_RCC2_R &= ~0x00000800;
}